Testable design methodology for clock domain crossing

摘要

A design methodology to debug synchronization of a signal crossing clock domains. A testable synchronization control logic utilizes a programmable register to set parameters to test signals traversing from one clock domain to another clock domain across a synchronization circuit. The register is programmed with a latency value that corresponds to a correct synchronization timing for the clock domain crossing. Other bit entries in the register provide setting of other debug parameters and indications of monitored results.