| 摘要 |
Disclosed is a communication circuit including a clock selection circuit ( 20 ) which receives CDR multiple-phase clocks ( 16 ) from a PLL ( 1 ) to a CDR circuit ( 7 ), selects one of the CDR multiple-phase clock signals ( 16 ) responsive to a clock selection signal ( 21 ), and outputs the selected clock signal. At a time of the loopback test, the clock signal selected by the clock selection circuit ( 20 ) is used as a transmit clock ( 11 ). Transmit data is looped back from an input/output terminal ( 4 ) to a receiver circuit ( 6 ). Data from the receiver circuit ( 6 ) is supplied to the CDR circuit ( 7 ), and comparison between recovered data from the CDR circuit ( 7 ) and expected value data is made by a comparison circuit ( 8 ), thereby conducting the test. By changing a phase of the transmit clock ( 11 ) by the clock selection circuit ( 20 ), a delay time (=tTx+tRx) which is a sum of a transmit circuit delay time (tTx) and a receiver circuit delay time (tRx) can be varied.
|
