发明名称 |
Architecture to monitor isolation integrity between floating gate and source line |
摘要 |
A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.
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申请公布号 |
US7226828(B2) |
申请公布日期 |
2007.06.05 |
申请号 |
US20040833179 |
申请日期 |
2004.04.27 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
HSIEH CHANG-JEN;SUNG HUNG-CHENG;HSU TE-HSUN |
分类号 |
H01L21/8238;H01L21/28;H01L21/336;H01L21/8247;H01L23/544;H01L27/115 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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