发明名称 Current source architecture for memory device standby current reduction
摘要 A memory device ( 200 ) can include a memory cell block ( 202 ), a standby current source ( 206 ), an active current source ( 208 ), and a clamping device ( 212 ). In a standby mode, a standby current source ( 206 ) can provide constant standby current I<SUB>STBY </SUB>to memory cell block ( 202 ) via block supply node ( 204 ). In an active mode, active current source ( 208 ) can provide current to accommodate current necessary for active operations (e.g., accessing the memory cell block). A clamping circuit ( 212 ) can provide additional current in the event a block supply node ( 204 ) potential VCCX collapses due to the presence of micro-defects. In addition, compensation for process variation can be achieved by a self regulating well ( 454 ) to source ( 404 ) back bias that can modulate the threshold voltage of p-channel transistors of memory cells within the well ( 454 ), reducing overall leakage.
申请公布号 US7227804(B1) 申请公布日期 2007.06.05
申请号 US20040827785 申请日期 2004.04.19
申请人 CYPRESS SEMICONDUCTOR CORPORATION 发明人 KOTHANDARAMAN BADRINARAYANAN;MANN ERIC;RODGERS THURMAN J.
分类号 G11C5/14 主分类号 G11C5/14
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