| 摘要 |
An HVS(High Voltage Stress) test circuit using a PLL(Phase Locked Loop) and a test method are provided to increase frequency in a semiconductor memory device without the limit of frequency specifications of a tester device and to improve the early fail detection rate by increasing screening performance, thereby securing the high quality and shortening the test time. An HVS test circuit(200) using a PLL(220) is composed of a level shifter(210) for shifting the level of signals(D,DB) input from a tester device; the PLL for frequency-multiplying the output of the level shifter; and a cut-off unit(230) for receiving the output of the PLL and applying or cutting off test signals(Q,QB) toward a DUT(Device Under Test) in response to control signals(CUTOFF,CUTOFFB). |
