| 摘要 |
PURPOSE:To obtain a proper clock signal from a digitally modulated signal by providing a clock generating circuit, phase decision circuit, and clock phase inverting circuit. CONSTITUTION:A decision window signal (f) is inputted from a clock phase decision window detecting circuit 51 to the clock phase decision circuit 54 to decide on whether a digital signal (g) is 0 or 1 when the signal (f) is at a level 1. The circuit 54 decides that the phase of a synchronizing clock signal (j) used by demodulating circuit 52 for demodulation is not proper when the digital signal (g) is 1, and outputs a phase inversion signal (h) to the clock phase inverting circuit 55. On receiving the phase inversion signal (h), the circuit 5 inverts the phase of the synchronizing clock signal (j) being inputted from a frequency dividing circuit 56 to correct the phase of the clock. Therefore, a synchronizing clock (i) applied to the demodulating circuit 52 has the proper phase. |
