发明名称 OPTIMIZATION APPARATUS AND METHOD FOR LOGIC DESIGN
摘要 PROBLEM TO BE SOLVED: To reduce circuit area by specifying any non-operational description within a circuit on the basis of test bench information used in circuit simulations, and deleting that portion. SOLUTION: An optimization apparatus for logic designs comprises a means for extracting descriptions that control circuit operation described within circuit information, a means for extracting signals that propagate from the test bench information to the operation control descriptions as control pattern information, a means for specifying non-operational control descriptions from the control description information and the control pattern information, and a means for deleting the non-operational control descriptions, thereby automatically creating optimal circuit information for which the circuit area has been reduced. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007133451(A) 申请公布日期 2007.05.31
申请号 JP20050322967 申请日期 2005.11.08
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TAKAHASHI HIROSHI;MISHIMA HIDEKI
分类号 G06F17/50 主分类号 G06F17/50
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