发明名称 PATTERN LAYOUT OF WORLD LINE TRANSFER TRANSISTORS IN NAND FLASH MEMORY WHICH EXECUTES SUBBLOCK ERASE
摘要 A semiconductor device includes a memory cell array, first word lines, second word lines and interconnection switching region. The memory cell array includes electrically rewritable nonvolatile memory cells. Each first word line is connected in common to memory cells of a corresponding row. Second word lines correspond to the respective first word lines. The second word lines are formed of a second interconnection of a layer different from that of the first interconnection. An interconnection switching region is provided between the first word lines and the second word lines. The interconnection switching region connect selected portions of the first interconnection and the second interconnection. The interconnection switching region has a multilayered interconnection structure in which the first word lines cross the second word lines to change at least part of layout positions.
申请公布号 US2007121385(A1) 申请公布日期 2007.05.31
申请号 US20070627727 申请日期 2007.01.26
申请人 发明人 FUTATSUYAMA TAKUYA
分类号 G11C11/34 主分类号 G11C11/34
代理机构 代理人
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