| 摘要 |
Embedded testing circuit for testing a dual port memory having a memory cell array being accessible through a first port (A) and a second port (B), said embedded testing circuit comprising an embedded address generation circuit for generating an internal address consisting of an internal row selection address (RSA<SUB>int</SUB>) and an internal column selection address (CSA<SUB>int</SUB>) in response to an external address consisting of an external row selection address (RSA<SUB>ext</SUB>) and an external column selection address (CSA<SUB>ext</SUB>), wherein said internal row selection address (RSA<SUB>int</SUB>) for addressing a second row of said memory cell array through said second port (B) is generated by an adder which increments the external row selection address (RSA<SUB>ext</SUB>) for addressing a first row of said memory cell array through said first port (A), such that the first row and said second row form adjacent rows within said memory cell array, wherein said internal column selection address (CSA<SUB>int</SUB>) for addressing a column of said memory cell array through said second port (B) is switchable to be identical to said external column selection address (CSA<SUB>ext</SUB>), and an embedded data generation circuit for generating an internal test data pattern in response to an external test data pattern, wherein said external test data pattern for accessing said memory cell array through said first port (A) is switchable to be inverted by an inverter when said memory cell array is accessed through said second port (B).
|
