| 摘要 |
A circuit arrangement for buck converters has a multiplicity of half bridges ( 10, 11 ). Each half bridge ( 10, 11 ) contains a first chip (HS<SUB>1</SUB>, HS<SUB>2</SUB>, HS<SUB>3</SUB>, HS<SUB>4</SUB>) and a second chip (LS<SUB>1</SUB>, LS<SUB>2</SUB>, LS<SUB>3</SUB>, LS<SUB>4</SUB>) , the first chip (HS<SUB>1</SUB>, HS<SUB>2</SUB>, HS<SUB>3</SUB>, HS<SUB>4</SUB>) and the second chip (LS<SUB>1</SUB>, LS<SUB>2</SUB>, LS<SUB>3</SUB>, LS<SUB>4</SUB>) in each case having a vertical power transistor. The load paths of the power transistor of the first chip (HS<SUB>1</SUB>, HS<SUB>2</SUB>, HS<SUB>3</SUB>, HS<SUB>4</SUB>) and of the power transistor of the second chip (LS<SUB>1</SUB>, LS<SUB>2</SUB>, LS3, LS<SUB>4</SUB>) are connected in series. The control inputs (G<SUB>1</SUB>, . . . , G<SUB>8</SUB>) of the power transistors can be driven individually. The half bridges ( 10, 11 ) are jointly accommodated in a semiconductor package and the first chip (HS<SUB>1</SUB>, HS2, HS3, HS<SUB>4</SUB>) and the second chip (LS<SUB>1</SUB>, LS<SUB>2</SUB>, LS3, LS<SUB>4</SUB>) lie above one another in each half bridge ( 10, 11 ).
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