发明名称 LAYOUT ANALYSIS METHOD AND LAYOUT ANALYSIS APPARATUS FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a layout analysis method and a layout analysis apparatus, for generating physical parameter distribution for accurately understanding, by a simulation, variation of transistor characteristics due to systematic fluctuations, by improving analysis precision for the transistor characteristics. SOLUTION: The variation distribution of systematic physical parameters dependent on layout is formed into a table, and held. A designed layout pattern is analyzed to select a corresponding table, and the physical parameter distribution 15 is generated based on the table. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007133498(A) 申请公布日期 2007.05.31
申请号 JP20050323807 申请日期 2005.11.08
申请人 FUJITSU LTD 发明人 INOUE YOSHIO;YONEDA TAKASHI;ITO MASARU
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04 主分类号 G06F17/50
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