PLL FREQUENCY SYNTHESIZER

摘要

PROBLEM TO BE SOLVED: To provide a PLL frequency synthesizer that can be applied to a complicated frequency, where a channel frequency is expressed by the sum of an integer and a fraction.

SOLUTION: The PLL frequency synthesizer has a multiple loop configuration. The synthesizer comprises a main loop 10 for setting the comparison frequency of the integers in an output frequency, and a subloop 15 for setting that of the fractions in the output frequency. The frequency becomes the sum of the integers in the output frequency set by the main loop 10 and the fractions in the output frequency set by the subloop 15, and is outputted as the output frequency.

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