| 摘要 |
A circuit arrangement for reading out data time delayed from a semiconductor memory comprises a common data input at which read data, which are read out of a semiconductor memory, are present and a data buffer FIFO for buffering the read data. The buffer FIFI comprises a plurality of FIFO modules each comprising a plurality of individual FIFO cells. Each FIFO module can be addressed via respective allocated first input and output pointers and each FIFO cell can be addressed via respective allocated second input and output pointers. The circuit arrangement further comprises a controllable read latency generator generating the first and second output pointers for driving the FIFO modules and FIFO cells with a read latency predetermined with reference to the first and second input pointers, respectively, and a common data output at which the read data are present time-delayed in dependence on the predetermined read latency.
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