Methods and apparatus for performing error correction code (ECC) coding techniques for high-speed implementations. The ECC code word is structured to facilitate a very fast single-error-detect (SED) that allows state machines to be stopped within a single cycle when an error is detected and enables a corresponding single-error-correct (SEC) operation to be performed over multiple cycles while the state machines are in a suspended mode.
申请公布号
WO2007061703(A2)
申请公布日期
2007.05.31
申请号
WO2006US44252
申请日期
2006.11.13
申请人
INTEL CORPORATION;GALBI, DUANE, E.;LOBOPRABHU, RANJIT;NIELL, JOSE