| 摘要 |
A memory cell having a low current memory device and a relatively high current output amplifier device, all built in the areawise footprint occupied by the memory device only. The low current memory device is a layered n-MOS or p-MOS lateral device having laterally spaced source and drain electrodes in a substrate and floating and control gates above the source and drain. The relatively high current output amplifier device is formed by contacts with layers or regions within layers having opposite conductivity types such that p-n junctions are arranged in forward and reverse bias configurations. These configurations form a vertical bipolar transistor that is beneath at least a portion of the lateral memory device and within the same footprint. The vertical bipolar transistor is connected as an output driver or amplifier for the memory device. An array of similar devices forms a memory array. The memory device can be a single transistor flash device or a single transistor EEPROM with a select transistor or other MOS memory device configuration.
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