发明名称
摘要 An input first stage is used for inputting both addresses and address keys. A test mode setting circuit and a function setting circuit are disposed between the input first stage and an address buffer. Each function setting mode buffer latches an internal address signal when a signal/RAS falls. Further, a function signal generating circuit is initialized by a power-on reset signal when a power supply is turned on.
申请公布号 JP3919847(B2) 申请公布日期 2007.05.30
申请号 JP19960134779 申请日期 1996.05.29
申请人 发明人
分类号 G11C11/413;G11C29/14;G11C8/06;G11C11/401;G11C29/00;G11C29/46 主分类号 G11C11/413
代理机构 代理人
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