Semiconductor integrated circuit operable as a phase-locked loop

摘要

A semiconductor integrated circuit (30) including a unit circuit (20) which constructs at least one part of a phase-locked loop and operates as a clock recovery circuit to generate a synchronized oscillation signal based on input data, and retiming means (30A) which generates recovery data by said oscillation output signal from said input data. The retiming means (30A) comprises:
- a pulse generating circuit (306) detecting a level transition of said input data and generating a detected pulse (306a) having a pulse width ´t to be provided to said unit circuit (20);
- a delay circuit (307) delaying said input data by a given delay time determined based on said pulse width ´t in order to provide delayed data (307a); and
- a retiming circuit (308) carrying out a retiming operation for said delayed data (307a) by one of a leading edge and a trailing edge of said synchronized oscillation signal (203a) in order to generate said recovery data.