| 摘要 |
<p>Disclosed is a countermeasure to be taken when a fault occurs in one of process modules 11 - 17 or a transport module 20 that makes it impossible to transport substrates to a process module positioned downstream of a post-exposure baking module 15 in accordance with a predetermined transport schedule in a post-exposure substrate transport path that starts from an exposure apparatus 5 and goes through the post-exposure baking (PEB) module 15 , a developing module 12 , and a post-development baking module 15 . In this instance, part of post-exposure processes to a post-exposure baking process are continuously performed to the exposed substrates and the wafers W having been subjected to the PEB process are loaded into a buffer module 32 and temporarily stored in the buffer module 32 until the fault is cleared. This prevents increase in the time period from an exposure process completion to the post-exposure baking process even when the fault occurs, thereby avoiding defective line width the circuit pattern of a resist, particularly a chemically amplified resist.</p> |
