发明名称 Analog-to-digital converter in which settling time of amplifier circuit is reduced
摘要 A first amplifier circuit samples an input analog signal and holds the sampled signal for a predetermined period of time. A first analog-to-digital converter circuit samples the input analog signal and converts the sampled signal into a digital value of a predetermined number of bits. A first digital-to-analog converter circuit converts an output signal from the first analog-to-digital converter circuit into an analog signal. A first subtracting amplifier circuit with a capacitively coupled input receives a signal at one end of a capacitor connected to an input terminal of the subtracting amplifier circuit and which samples a signal occurring at the other end of the capacitor, the subtracting amplifier circuit subtracting an output signal from the first digital-to-analog converter circuit from an output signal from the first amplifier circuit, The first digital-to-analog converter circuit outputs the analog signal to the capacitor before a first switch is turned on, in order to adjust charges stored in the capacitor.
申请公布号 US7224306(B2) 申请公布日期 2007.05.29
申请号 US20050299741 申请日期 2005.12.13
申请人 SANYO ELECTRIC CO., LTD. 发明人 KOBAYASHI SHIGETO
分类号 H03M1/12 主分类号 H03M1/12
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