| 摘要 |
An active-matrix substrate is provided, which suppresses the unevenness of its surface due to the height difference of the TFTs and gate and data lines from the remaining area. After TFTS, gate lines, and data lines are formed on a transparent base, a transparent dielectric layer is formed on the base to cover the TFTs, the gate lines, and the data lines. The dielectric layer is selectively etched to form transparent dielectric portions arranged in a matrix array in such a way as to form a first plurality of recesses extending along the respective gate lines and a second plurality of recesses extending along the respective data lines. Each of the portions has a thickness equal to or greater than the maximum height of the TFTs, the gate lines, or the data lines, and a distance equal to or greater than the thickness thereof from a corresponding one of the TFTs, the gate lines, or the data lines. A planarization layer is then formed to fill at least the first plurality of recesses and the second plurality of recesses. Pixel electrodes are arranged on or over the flat surfaces of the respective portions. The connection part of each pixel electrode is connected to a corresponding one of the TFTs by way of a corresponding one of holes of the planarization layer.
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