发明名称 INDIVIDUAL BIT LINE RECOVERY CIRCUITS
摘要 8332-246 / NS1527 INDIVIDUAL BIT LINE RECOVERY CIRCUITS A bipolar recovery circuit for a static random access memory cell is described. The circuit corrects reverse emitter-base breakdown which occurs in the known common base node writing recovery circuits. The circuit is simple, requiring little silicon chip area to fabricate. In a preferred embodiment, a separate recovery circuit is coupled to each of the true output line and the complement output line of the memory cell.
申请公布号 CA2043928(A1) 申请公布日期 1991.12.07
申请号 CA19912043928 申请日期 1991.06.05
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 KERTIS, ROBERT A.
分类号 G11C11/417;G11C7/12;G11C11/419;(IPC1-7):G11C7/00;G11C11/41 主分类号 G11C11/417
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