| 摘要 |
A digital filter realization is proposed that consists of only one multiplier, i. e. which operates with a higher clock rate and changes coefficient at the multiplier each clock cycle, but in which the clock rate of the multiplier is reduced in comparison to prior art filters by considering equal filter coefficients, e. g. based on the symmetry of FIR filter coefficients. According to the present invention preferably the samples belonging to equal filter coefficients are added in advance in order to reduce the number of multiplications, which concludes in a reduced clock rate for the filter, a reduced needed calculation power, and therefore a reduced power consumption.
|
