| 摘要 |
A reference fail bit verifying circuit with different reference fail bit numbers for different modes and a non-volatile semiconductor memory device having the circuit are provided to reduce total lead time in a data erase operation, by easily setting proper reference fail number in a first mode and a second mode. In a reference fail bit verifying circuit(100), a fail bit counter(110) generates a first counting signal and a second counting signal by counting the detection of a fail bit, and the first and second counting signals are enabled in response to the detection of the corresponding number of the fail bits, respectively. A bit verifying block(BKFB) generates a reference bit verifying signal enabled in response to the transition of the first and second counting signals, and the reference bit verifying signal responds to the enabling of the first counting signal in a first mode and responds to the enabling of the second counting signal in a second mode. The bit verifying block includes a fail bit verifying part(130) generating a setting bit verifying signal enabled in response to the transition of the first and second counting signals.
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