发明名称 DUAL PATH REDUNDANCY WITH STACKED TRANSISTOR VOTING
摘要 PROBLEM TO BE SOLVED: To provide a method of operation and an apparatus for radiation hardening a combinational logic circuit. SOLUTION: A section of logic that is to be radiation hardened is identified. An entire logic circuit or a portion of the logic circuit may be radiation hardened. Once the section of logic is identified, a Field Effect Transistor (FET) is duplicated so as to create a voter FET. The voter FET is coupled with an original node (or signal) and a duplicated node (or signal). If a radiation event strikes either the original node or the duplicated node, the voter FET will prevent an upset from propagating to down stream logic by preventing a conduction path through the voter FET. Additionally, all of the circuitry that was duplicated in order to create the duplicated node may also undergo a radiation event without causing an upset to propagate to downstream logic. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007129689(A) 申请公布日期 2007.05.24
申请号 JP20060211811 申请日期 2006.08.03
申请人 HONEYWELL INTERNATL INC 发明人 FRIEDMAN MARK E
分类号 H03K19/20;H01L21/822;H01L27/04;H03K19/003 主分类号 H03K19/20
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