| 摘要 |
PROBLEM TO BE SOLVED: To configure a decoding signal circuit to generate a dual operation decoding signal that enables a memory device to perform a read operation and a write operation in one clock cycle. SOLUTION: The decoding signal circuit generates a dual operation decoding signal, thereby enabling a memory device to perform a read operation and a write operation in one clock cycle. The decoding signal circuit is configured such that a read decoding signal and a write decoding signal are generated and multiplexed together to form the dual operating decoding signal. The memory device receives a read address and a write address consecutively in one cycle to generate the dual operation decoding signal. A single operation, such as a read only operation or a write only operation, can be performed as well as the dual operation of performing the read operation and the write operation in the same cycle. COPYRIGHT: (C)2007,JPO&INPIT
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