| 摘要 |
The invention relates to a vertical field-effect transistor. It comprises an island ( 12 ) of doped single-crystal semiconductor material, comprising a drain region ( 15 ) and a drain contact region ( 17 ) placed laterally with respect to the drain region, and above the island, a source region ( 38 ) and several vertical parallel channels ( 36 ) made of a lightly-doped single crystal semiconducting material, which extends vertically between the drain region and the source region and each channel being completely surrounded by an insulating sheath ( 46 ), and the space that separates the channels thus isolated from one another being filled with a conducting gate ( 50 ) each enclosing channels. The invention also relates to a novel fabrication process using a sacrificial gate layer whose thickness defines the length of the channel.
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