摘要 |
Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way predictor, a policy counter, and a cache refill circuit. The policy counter provides a signal to the way predictor that determines whether the way predictor operates in a first mode or a second mode. Following a cache miss, the cache refill circuit selects a way of the cache and compares a layer number associated with a dataram field of the way to a way-set-layer number. The cache refill circuit writes a block of data to the field if the layer number is not equal to the way-set-layer number. If the layer number is equal to the way-set-layer number, the cache refill circuit repeats the above steps for additional ways until the block of memory is written to the cache. |