| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To increase data input/output speed under environment in which speed of a memory cell array access clock is restricted. <P>SOLUTION: The memory device includes a plurality of word lines, a memory cell array including a plurality of column lines and a plurality of memory cells, a row decoding section, a K bit prefetch section, and an output buffer section. The row decoding section decodes a row address in response to a first clock to activate one of word lines corresponding to the decoded row address. The K-bit prefetch section decodes a column address in response to a second clock for accessing the memory cell array, and prefetches K data corresponding to the column address decoded from the memory cell connected to the activated word line. A frequency of the second clock is 1/M of that of the first clock, M is a real number other than a power of 2, and K is a natural number of 2 or more. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
