| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an information processing system capable of shortening a processing period of time and easily reducing power consumption, and to provide a method for controlling the information processing system. <P>SOLUTION: This information processing system 1 is provided with: a bus 3; an I/O 30 for USB; an I/O 40 for UART; a DMAC 20; a bus arbitration circuit 70; and a clock frequency-dividing circuit 80. The I/O 30 for USB and the I/O 40 for UART output a DMA request signal. The DMAC 20 outputs a bus right request first signal based on the DMA request signal. The bus arbitration circuit 70 outputs a bus right permission first signal based on the bus right request first signal. The DMAC 20 outputs the DMA permission signal to an input/output device based on the bus right permission first signal. A clock frequency-dividing circuit 80 determines a clock frequency based on the bus right permission first signal and the DMA permission signal. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
