| 摘要 |
PROBLEM TO BE SOLVED: To provide a bus arbitration circuit capable of shortening transfer time of bus use right. SOLUTION: In the bus arbitration circuit constituted so that a plurality of series of bus acquisition signal generation circuits (2-0, ..., 2-N) are serially connected so as to individually input bus acquisition length information respectively outputted from a plurality of bus acquisition length information output parts (1-0, ..., 1-N), and further constituted so that each of the plurality of series of bus acquisition signal generation circuits (2-0, ..., 2-N) outputs a bus arbitration pulse generated on the basis of a bus arbitration pulse inputted from the preceding bus acquisition signal generation circuit to the succeeding stage in accordance with the inputted bus acquisition length information to form a bus arbitration pulse for the succeeding bus acquisition signal generation circuit and a bus arbitration pulse of the final bus acquisition signal generation circuit is used as a bus arbitration pulse of the initial bus acquisition signal generation circuit; bus release timing and a bus arbitration pulse to be transferred to the succeeding bus acquisition signal generation circuit are generated. COPYRIGHT: (C)2007,JPO&INPIT
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