发明名称 |
Double-extension formation using offset spacer |
摘要 |
A MOS transistor structure is disclosed. A gate electrode is disposed on a semiconductor substrate. A first extension of a predetermined impurity type is substantially aligned with the gate electrode in the substrate. A second extension of the predetermined impurity type overlaps with the first extension in the substrate. The first extension has at least one lateral boundary line closer to the gate electrode than that of the second extension. Source and drain regions of the predetermined polarity type overlaps with the first and second extensions in the substrate. The second extension has at least one lateral boundary line closer to the gate electrode than that of the source and drain regions. The source and drain regions are deeper than the second extension, which is deeper than the first extension, so that they collectively reduce lateral abruptness of the source and drain, while maintaining a reduced extension resistance.
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申请公布号 |
US2007114604(A1) |
申请公布日期 |
2007.05.24 |
申请号 |
US20050286003 |
申请日期 |
2005.11.22 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
HUANG HUAN-TSUNG;HAN LIANG-KAI |
分类号 |
H01L21/336;H01L29/76 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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