MULTI-PORT HIGH-LEVEL CACHE UNIT AND A METHOD FOR RETRIEVING INFORMATION FROM A MULTI-PORT HIGH-LEVEL CACHE UNIT

摘要

A device (8) that includes multiple processors (110, 112, 114, 118) that are connected to multiple level- one cache units (111, 113, 1115, 119) . The device (8) also includes a multi-port high-level cache unit (9) that includes a first modular interconnect (100), a second modular interconnect (100'), multiple high- level cache paths (10, 10'); whereas the multiple high-level cache paths (10, 10') comprise multiple concurrently accessible interleaved high-level cache units (14, 14') . Conveniently, the device also includes at least one non-cacheable path. A method (900) for retrieving information from a cache that includes: (i) concurrently receiving (910), by a first modular interconnect of a multiple-port high-level cache unit (9), requests to retrieve information. The method (900) is characterized by providing (920) information from at least two paths out of multiple high-level cache paths if at least two high-level cache hit occurs, and providing information via a second modular interconnect if a high-level cache miss occurs .