DATA PROCESSING APPARATUS AND METHOD

摘要

A vector shuffle unit (50) comprises a number of base multiplexer units (mux0, muxl, mux2, mux3), which are connected to an output multiplexer (11). The vector shuffle unit (50) can be configured to shuffle a vector having any one of a number of different element sizes (for example 8, 16 and 32 bit element sizes). A power saving circuit (15) is provided for reducing the power consumption in the base multiplexer units muxl, mux2 and mux3, by masking the inputs to these multiplexer units when performing shuffle operations on certain element sizes. For example, no masking is required for mux0 as it is always needed for each of the 8, 16 and 32 bit element sizes. Multiplexer units muxl and mux3 are only used for 8 bit elements and can be masked together as they are always used together. Mux2 is only used for 8 and 16 bit elements and requires its own power saving circuitry.