| 摘要 |
<P>PROBLEM TO BE SOLVED: To allow each memory array to operate independently, and eliminate bus arbitration between a plurality of CPU chips when memories are integrated by providing a plurality of memory arrays in one chip in a system in which the plurality of CPU chips use a plurality of memories. <P>SOLUTION: A plurality of memory arrays 10, 20 are provided in the same memory chip 1, and a data system circuit, an address system circuit, and a control system circuit are independently provided in each memory array. On the other hand, a data terminal 42 for connection to the outside of a chip, an address terminal 40, and a control terminal 41 are shared between memory arrays 10 and 20. Data, addresses and control signals are distributed to memory arrays 10 and 20 via three MUXs of signal selection circuits controlled by an array selection signal ASEL (clock). A signal is supplied to one memory array 10 at a rising edge of the clock, and a signal is applied to the other memory array 20 at a falling edge. <P>COPYRIGHT: (C)2007,JPO&INPIT |
