| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor evaluation device for decreasing a cache hit rate without operating the flash operation of a cache memory. SOLUTION: The processor evaluation device performs evaluation while considering a cache hit rate to a cache memory. wherein, an access counter circuit 202 counts the frequency of memory access to be performed to the cache memory by the processor, a comparator circuit 203 compares the counted frequency of the memory access with a cache mistake point signal 26 showing the generation frequency of the cache mistake, a selector 201 changes an address 22 to be output by the processor to a dummy base address 24 generating a cache mistake, and on the basis of the changed address, a hit mistake determination circuit determines whether or not the cache memory has been hit. COPYRIGHT: (C)2007,JPO&INPIT
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