发明名称 Method and apparatus for integrated circuit fault isolation and failure analysis using linked tools cockpit
摘要 A microelectronic circuit debugging environment links development tools by correlating a selected element in a first tool with elements in the datasets of other tools. A signaling module instructs the other tools to display the correlated elements.
申请公布号 US2007118827(A1) 申请公布日期 2007.05.24
申请号 US20050285403 申请日期 2005.11.21
申请人 RAHMAN ASIFUR 发明人 RAHMAN ASIFUR
分类号 G06F17/50 主分类号 G06F17/50
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