<p>A memory cell region (mmry) is provided with a memory cell array wherein a plurality of memory elements (R) are arranged in matrix. The memory element has a chalcogenide material storage layer (22) for storing a high resistance status having a high electrical resistance and a low resistance status having a low electrical resistance by atomic arrangement change. A logical circuit region (lgc) is provided with a semiconductor integrated circuit. The memory cell region and the logical circuit region are formed on the same semiconductor substrate (1). The chalcogenide material storage layer (22) is composed of a chalcogenide material including at least a Ga or an In of 10.5 atom% or more but not more than 40 atom%, a Ge of 5 atom% or more but not more than 35 atom%, a Sb of 5 atom% or more but not more than 25 atom% and a Te of 40 atom% or more but not more than 65 atom%.</p>
