摘要 |
<p>This invention provides a semiconductor device comprising a memory cell array and a semiconductor integrated circuit which are provided together on an identical semiconductor substrate (1). The memory cell array is provided in a memory cell region (mmry) and comprises a plurality of memory devices (R), provided in a matrix form, each comprising a chalcogenide material storage layer (22) for storing a high electric resistance state and a low electric resistance state by taking advantage of a change in atomic arrangement. The semiconductor integrated circuit is provided in a logic circuit region (lgc). The chalcogenide material storage layer (22) is formed of a chalcogenide material comprising not less than 7 atomic% and not more than 40 atomic% of at least one of Ga and In, not less than 5 atomic% and not more than 35 atomic% of Ge, not less than 5 atomic% and not more than 25 atomic% of Sb, and not less than 40 atomic% and not more than 65 atomic% of Te.</p> |
申请人 |
RENESAS TECHNOLOGY CORP.;MORIKAWA, TAKAHIRO;TERAO, MOTOYASU;TAKAURA, NORIKATSU;KUROTSUCHI, KENZO |
发明人 |
MORIKAWA, TAKAHIRO;TERAO, MOTOYASU;TAKAURA, NORIKATSU;KUROTSUCHI, KENZO |