| 摘要 |
<p>In a clock data restoration device (1), respective phases of clock signals CKXA, CKXB, and CK are adjusted so as to coincide with the phases of input digital signals by a process in a loop including a sampler unit (10), a detection unit (20), a timing decision unit (30), and a clock output unit (40). A sampling time of the digital signal indicated by the clock signal CKXA is adjusted to coincide with the peak time of distribution of data transition time when the values of the two bits immediately before D(n - 2) and D(n - 1) are different from each other. A sampling time of the digital signal indicated by the clock signal CKXB is adjusted to coincide with the peak time of distribution of data transition time when the values of the two bits immediately before D(n - 2) and D(n - 1) are identical to each other.</p> |
