| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a reconfigurable network to be mounted on a chip which minimizes a configuration waiting time of a reconfigurable execution unit and is reconfigurable in progress. <P>SOLUTION: The reconfigurable network on the chip includes a general purpose microprocessor, a plurality of on-chip memories, a plurality of reconfigurable execution units including a logic array which is reconfigurable and programmable individually, a plurality of configurable system interface units to provide an interconnection between the on-chip memory and the network or a bus, an on-chip network including a network interconnection interface, a fine-grain interconnection unit to collect input/output signals related to a specific interface and to give them to a designated system interface resource, and a plurality of input/output blocks to supply a link between external networks or between device interfaces. <P>COPYRIGHT: (C)2007,JPO&INPIT |
