Circuit for Input-Output Buffer of Register Delay locked loop,申请号KR20010015141-传众专利搜索

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发明名称	Circuit for Input-Output Buffer of Register Delay locked loop
摘要
申请公布号	KR100721187(B1)	申请公布日期	2007.05.23
申请号	KR20010015141	申请日期	2001.03.23
申请人		发明人
分类号	G11C11/407	主分类号	G11C11/407
代理机构		代理人
主权项
地址

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