发明名称
摘要 PROBLEM TO BE SOLVED: To provide a failure detecting method capable of detecting failure of a timer and a bus line between a timer and capture resistor at low cost without enlarging the scale of a circuit for failure detection, and not requiring an interrupt signal confound with an original interrupt signal. SOLUTION: A second timer T2 is provided in a capture circuit outputting interrupt (q) when a capture resistor R latches the value of a first timer T1, and at generating the interrupt (q), the value of the capture resister and the value of the second timer T2 are read, and when the difference is not received in a fixed range, it is judged to be a failure. Hereby, the failure detecting method detecting a failure of the bus line and not requiring interrupt is provided.
申请公布号 JP3918276(B2) 申请公布日期 2007.05.23
申请号 JP19980028655 申请日期 1998.02.10
申请人 发明人
分类号 G01R31/00;B60T8/88;G01M17/007;G01P3/42;G04C10/04;H03K21/40 主分类号 G01R31/00
代理机构 代理人
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