发明名称 Fast-locking digital phase locked loop
摘要 A method and apparatus for synchronizing signals. For devices, such as memory devices, implementing a synchronization device to synchronize signals, a synchronization device having a delay locked loop coupled to a phase locked loop may be implemented. The delay locked loop is implemented to measure the period of a reference signal and to mirror the period into a second delay line such that an adjusted reference signal having a frequency approximately equal to the frequency of the reference clock may be generated. The adjusted reference signal is delivered to an oscillator such that the oscillator begins oscillating at approximately the same frequency as the reference clock signal to provide a fast locking synchronization device.
申请公布号 US7221201(B2) 申请公布日期 2007.05.22
申请号 US20040915774 申请日期 2004.08.11
申请人 MICRON TECHNOLOGY, INC. 发明人 LIN FENG;KEETH BRENT
分类号 H03L7/06 主分类号 H03L7/06
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