发明名称 Single NMOS device memory cell and array
摘要 The snapback characteristics of the parasitic NPN structure inside an NMOS device are used to write and store information in the device by periodically triggering the device from the high impedance state to the low impedance state using the self turn-on characteristics of the device under elevated voltage. To minimize power consumption, and thus overheating, in the "on" state, a pulsed mode operation is combined with dV/dt triggering powering the device at a constant Vdd pulse amplitude.
申请公布号 US7221608(B1) 申请公布日期 2007.05.22
申请号 US20040957986 申请日期 2004.10.04
申请人 NATIONAL SEMICONDUCTOR CORPORATION 发明人 VASHCHENKO VLADISLAV;HOPPER PETER J.;LINDORFER PHILIPP
分类号 G11C7/00 主分类号 G11C7/00
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