Cascaded gate-driven ESD clamp

摘要

A method is provided for semiconductor ESD protection in a mixed voltage device using a cascaded gate driven NMOS clamp circuit. Use of a bias circuit allows for an external I/O signal to have a voltage higher than the internal circuit power supply voltage so that a proper trigger level is provided in reference to an external power supply reference. A cascaded gate NMOS clamp circuit dissipates charge from an ESD event from the higher external I/O signal level without interfering with the normal operation of the internal or "core" circuits.