A TARGET CONTROLLER OF PERIPHERAL COMPONENT INTERCONNECTION HAVING VERSATILITIES IN DESIGN

摘要

A Peripheral Component Interconnection (PCI) target controller apparatus based on a PCI 2.x protocol (i.e., a PCI 2.1 protocol, a PCI 2.2 protocol, and a PCI 2.3 protocol) is disclosed. If a bus master requests a memory write command from a target device, the target device answers the memory write command, receives data from the bus master, and records the received data in a local device, or if the bus master requests a memory read command from the target device, the target device answers the memory read command, and reads data from the local device via a local bus. The target controller does not additionally include a pre-fetched memory or a internal FIFO (First In First Out) unit therein, but arranges the pre-fetched memory or the FIFO unit at an external part, such that a memory size can be selectively determined according to a request from an application board to be designed.