发明名称 |
Constant reconstructing processor which supports reductions in code size |
摘要 |
<p>A processor includes a constant register 36 for storing a constant, a format decoder 21 for decoding a format code located in the P0.0 field of an instruction stored in the instruction register 10, and a constant register control unit 32 which, when the format decoder 21 has decoded that the instruction includes a constant to be stored in the constant register 36, shifts the presently stored value in the constant register 36 and stores the constant into the constant register 36. <IMAGE></p> |
申请公布号 |
EP0897147(A2) |
申请公布日期 |
1999.02.17 |
申请号 |
EP19980304702 |
申请日期 |
1998.06.15 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
TAKAYAMA, SHUICHI;HIGAKI, NOBUO;TANAKA, TETSUYA;HEISHI, TAKETO;SUZUKI, MATSATO |
分类号 |
G06F9/30;G06F9/32;G06F9/38;G06F9/46;G06F15/00;(IPC1-7):G06F9/32 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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