发明名称 Method and apparatus for adaptive determination of timing signals on a high speed parallel bus
摘要 Methods and apparatus are provided for adaptive determination of timing signals, such as on a high speed parallel bus. The invention adaptively determines a timing signal having a first edge with respect to an internal clock, wherein the timing signal includes a period in which the timing signal is undriven, followed by a period immediately before a first transition in which the timing signal is in a predefined state. The timing signal is evaluated using one or more comparators; and an output of the one or more comparators are latched based on a clock signal. The clock signal is adjusted until the one or more comparators indicate the timing signal is in the known and valid state. The clock signal is further adjusted until the one or more comparators indicate the first transition has been reached. Thereafter, a gating control signal is established based on a timing of the first transition.
申请公布号 US7218557(B1) 申请公布日期 2007.05.15
申请号 US20050318952 申请日期 2005.12.23
申请人 AGERE SYSTEMS INC. 发明人 CHLIPALA JAMES D.;MOBIN MOHAMMAD S.
分类号 G11C8/18 主分类号 G11C8/18
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