发明名称 |
Digital delay locked loop capable of correcting duty cycle and its method |
摘要 |
An apparatus for adjusting a clock signal, including: a clock multiplexing unit for receiving an external clock signal, an external clock bar signal and a feed-backed clock signal in order to select one of the external clock signal and the external clock bar signal as an output signal of the clock multiplexing unit based on a result of comparing a phase of the external clock signal with a phase of the feed-backed clock signal; and a delay locked loop (DLL) for generating a duty corrected clock signal and the feed-backed clock signal in response to the output signal of the clock multiplexing unit.
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申请公布号 |
US2007103212(A1) |
申请公布日期 |
2007.05.10 |
申请号 |
US20060646054 |
申请日期 |
2006.12.27 |
申请人 |
LEE HYUN-WOO;KWAK JONG-TAE |
发明人 |
LEE HYUN-WOO;KWAK JONG-TAE |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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