发明名称 Memory circuit
摘要 There is provided a memory circuit including a first memory cell mapped on an address space accessible from a processor, and a second memory cell not mapped on the address space and having the same constitution as that of the first memory cell, wherein a control circuit for executing a control function relating to the memory circuit is included, and an output signal line of the second memory cell is connected to the control circuit.
申请公布号 US2007103954(A1) 申请公布日期 2007.05.10
申请号 US20060590803 申请日期 2006.11.01
申请人 IKEDA YUUICHIROU 发明人 IKEDA YUUICHIROU
分类号 G11C5/02 主分类号 G11C5/02
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